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| SL74LV374 OCTAL D-TIME FLIP-FLOP; POSITIVE EDGETRIGGER (3-StatE) SL74LV374 are compatible by pinning with SL74HC374 and SL74HCT374 series. Input voltage levels are compatible with standard CMOS levels. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS. * Supply voltage range from 2.0 to 3.2 V * LOW input current: 1.0 A; 0.1 A at O = 25 N * Output current 8 mA * Latch current value not less than 150 mA at O = 125 N * ESD acceptable values: not less than 2000 V as per HBM, and not less than 200 V as per MM ORDERING INFORMATION SL74LV374N Plastic DIP SL74LV374D SOIC TA = -40 to 125 C for all packages BLOCK DIAGRAM 03 04 07 08 13 14 17 18 11 02 05 06 09 12 15 16 D0 D1 D2 D3 D4 D5 D6 D7 CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 PIN ASSIGNMENT 01 02 03 04 05 20 19 18 17 16 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 374 06 07 08 09 10 15 14 13 12 11 19 Q7 OE 01 GND Pin 20=VCC Pin 10 = GND FUNCTION TABLE Inputs OE L L L H CP Dn H L X X Output Qn H L no change Z L, H, X SLS System Logic Semiconductor SL74LV374 ABSOLUTE MAXIMUM RATINGS* Symbol VCC IIK *1 IOK * IO * ICC IGND PD 2 3 Parameter Supply voltage Input diode current Output diode current Output source or sink current Bus driver outputs Ground current Power dissipation per package, Plastic DIP *4 SOIC *4 Storage temperature range Rating -0.5 to +5.0 20 50 35 70 70 750 500 -65 to +150 Unit V mA mA mA mA mA mW Tstg * C In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute maximum ratings functioning is guaranteed at the recommended operating conditions. *1 Provide VI < -0.5 V or VI > VCC + 0.5 V. *2 Provide VO < -0.5 V or VO > VCC + 0.5 V. *3 Provide -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70C to 125C power dissipation value decreases - for Plastic DIP by 12 mW/C - for SOIC by 8 mW/C RECOMMENDED OPERATING MODES Symbol VCC VIN VOUT TA tLH, tHL Supply voltage Input voltage Output voltage Operating ambient temperature range. For all types packages Input rise and fall times VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 Max 3.6 VCC VCC 125 1000 700 500 400 Unit V V V C ns SLS System Logic Semiconductor SL74LV374 DC CHARACTERISTICS Test Symbol Parameter coditions VCC, V 25C Limits -40C to 85C 125C Unit min max min max min max VIH HIGH level input VO = VCC-0.1 V voltage 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 3.6 3.6 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 0.1 0.5 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 1.0 5 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 1.0 10 V VIL LOW level input VO =0.1 V voltage V VOH HIGH level output voltage VI = VIH or VIL IO = -50 A V VI = VIH or VIL IO = -8 mA VOL LOW level output voltage VI = VIH or VIL IO = 50 A V V VI = VIH or VIL IO = 8 mA II IOZ Input leakage current Output OFFstate current Suply current VI = VCC eee 0V 3-state outputs VI = VIL or VIH VO =VCC or 0 V VI =VCC or 0 V IO = 0 A V A A ICC 3.6 - 8.0 - 80 - 160 A SLS System Logic Semiconductor SL74LV374 AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns) Test Symbol Parameter conditions VCC, V 25C Limits -40C to 85C 125C Unit min max min max min max tPHL, tPLH Propagation from CP to Qn delay tPHZ tPLZ Propagation from OE to Qn delay tPZH tPZL Propagation from OE to Qn delay tTHL, tTLH HIGH-to-LOW and LOW-toHIGH transition time Clock pulse width HIGH or LOW Set-up time Dn to CP Hold time Dn to CP Figure 1 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 2.0 3.0 3.0 3.0 250 18 11 45 13 8 25 5 5 180 45 27 160 38 25 160 38 23 75 16 10 27 46 7 34 350 23 14 50 17 10 25 5 5 230 56 34 200 57 36 200 48 29 100 20 13 22 37 540 28 17 100 20 12 25 5 5 270 68 41 240 68 43 240 58 35 120 24 15 18 31 MHz pF ns Figure 3 Figure 3 Figure 1 tW Figure 1 tSU Figure 2 tH Figure 2 fc CI CPD CP naximum Figure 1 pulse frequency Input capacitance Power VI = 0 V or VCC dissipation capacitance (per flip-flop) SLS System Logic Semiconductor SL74LV374 tLH 0.9 CP 0.1 V1 tW 1/fc tPHL tPLH 0.9 V1 Qn 0.1 tTLH V1 = 0.5V CC 0.9 V1 0.1 0V B V1 V1 GND VCC tTHL Figure 1- Time diagram VCC V1 V1 V1 V1 Dn GND tSU tH tSU tH VCC CP V1 V1 GND V1 = 0.5V CC Figure 2 - Time diagram SLS System Logic Semiconductor SL74LV374 tLH 0.9 OE V1 0.1 tPZH V1 V1 0.1 GND VOH tHL 0.9 VCC 0.9 tPHZ Qn 0V B tPLZ Qn V1 tPZL 0.1 VOL V1 = 0.5V CC VCC Figure 3 - Time diagram SLS System Logic Semiconductor SL74LV374 Drawing of the chip 1.66 mm 18 19 17 16 15 14 13 12 1.68 mm 20 11 74LV373/374 1 10 On-chip marking 2 9 7 8 3 4 5 6 Pads allocation Table Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 coordinates (counted from lower left corner), mm X Y 0.142 0.628 0.142 0.377 0.142 0.125 0.498 0.125 0.693 0.125 0.871 0.125 1.095 0.125 1.423 0.130 1.423 0.329 1.423 0.587 1.423 0.949 1.423 1.198 1.423 1.447 1.085 1.447 0.868 1.447 0.696 1.447 0.461 1.447 0.142 1.447 0.142 1.245 0.142 0.997 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 SLS System Logic Semiconductor SL74LV374 SLS System Logic Semiconductor |
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